A flash memory is a kind of programmable ROM (PROM) capable of electrically rewriting data. A flash memory is a combination of an erasable PROM (EPROM) and an electrically erasable PROM (EEPROM). In the EPROM, a memory cell includes a single transistor and has a small cell area, but data must be erased by ultraviolet rays. In the EEPROM, data can be erased electrically, but a memory cell includes two transistors and has a large cell area. The flash memory performs a program input like the EPROM and an erasure method like the EEPROM using a single transistor. A flash memory is called a “nonvolatile memory” because information memorized therein does not disappear even when a power source is turned off. In this respect, a flash memory differs from a dynamic RAM (DRAM), a static RAM (SRAM), or the like.
Flash memory may be classified into NOR array, in which cells are arranged in parallel between a bit line and a ground, and NAND array, in which cells are arranged in series between a bit line and a ground. Since NOR-type flash memory enables high-speed read access, it is widely used for booting a portable cellular phone. The NAND-type flash memory has a low read speed, but a high write speed. It is therefore suitable for storing data and advantageous for miniaturization. In addition, flash memory may be classified, based on the structure of a unit cell, into stack and split gate types. Flash may also be classified, based on the shape of a charge storage layer, into floating gate and silicon-oxide-nitride-oxide-silicon (SONOS) devices.
Memory cells in a NOR-type device are connected in parallel to a bit line. Therefore, if the threshold voltage of a cell transistor becomes lower than a voltage (generally, “zero” volt) applied to a control gate electrode of an unselected memory device, current is conducted between a source and a drain regardless of whether a selected memory device is turned on or off. This may result in an operational fault where all memory devices register an “on” value. Further, the NOR-type device will need a high-capacity boosting circuit in order to generate a voltage required for implementation of a program based on channel hot carrier injection.
To solve the above described problems, a gate structure that is generally referred to as a “split gate” may be used. FIG. 1 schematically illustrates a cross section of a unit cell transistor having a split gate with a double-poly structure. Referring to FIG. 1, a source diffusion region 12s and a drain diffusion region 12d are formed in an active region of a substrate 10. A floating gate 16 is formed above the substrate 10 in the vicinity of the drain diffusion region 12d by interposing a gate insulating layer 14. Also, a control gate 22 extends from the top of the floating gate 16 to the sidewall thereof such that one end of the control gate 22 is parallel to the substrate 10. The control gate 22 and the floating gate 16 are insulated from each other by an inter-gate insulating layer 18, and a tunnel insulating layer 20 is interposed between the substrate 10 and the control gate 22.
In a memory device having the above described split gate structure shown in FIG. 1, if voltages Vth and Vpp are applied to the control gate 22 and the drain region 12d, respectively, current is conducted from the source region 12s to the drain region 12d. As a result, electrons pass through the insulating layer and into the floating gate 16 under the influence of an electrostatic force from the floating gate 16. In this way, the flash can be programmed as desired. If a high voltage is applied to the control gate 22 and the source and drain regions 12s and 12d are grounded, the electrons are discharged from the floating gate 16. They escape from the floating gate 16 under the influence of the high voltage applied to the control gate 22 via Fowler-Nordheim (F-N) tunneling.
However, in the above described split gate device, since a channel of the control gate is formed with photolithography, it is difficult to accurately control a channel length. Therefore, a change of voltage and current inevitably occurs during an operation of the control gate. Furthermore, since the control gate, NMOS and PMOS read transistors, tunneling or carrier-injection regions, etc. are formed in parallel over a surface of the substrate, there is a limit to reduction in cell size.
As a result, the above described split gate device occupies a large area, and requires power lines for respective regions, resulting in a very complicated cell structure.